For isolating elements in a semiconductor device, a large number of junction isolating techniques using p-n junction have been used for a long time. In recent years, however, dielectric isolation wherein in an SOI (silicon on insulator) substrate having a buried insulating film, a trench that extends from the surface of the substrate to the buried insulating film is formed, and an insulating film is formed in the trench, has been used.
Such an element structure of SOI-trench isolation is especially effective in semiconductor devices for high breakdown voltage power fields wherein the formation of deep isolation is generally required. This is because although there was disadvantage wherein the area occupied by the isolation region was large compared with the area of the element in the case of using p-n junction isolation in semiconductor devices for high breakdown voltage power fields, the use of SOI-trench isolation enables the reduction of the area of the isolation region. As a result, the areas for product chips can be reduced, and cost reduction can be expected. Furthermore, there is also advantage wherein there are no cross-talks between elements, and a plurality of high breakdown voltage power elements, which are output sections, and a plurality of low breakdown voltage elements, which are driving circuit sections thereof can be easily mounted together in the same chip.
For the above-described reasons, high breakdown voltage power elements formed on an SOI substrate have attracted attention. One of such high voltage semiconductor elements of an insulated gate type is an IGBT. The IGBT is a high voltage semiconductor element having both the high-speed switching characteristics of a power MOS transistor and the high-output characteristics of a bipolar transistor, and is widely utilized in recent years in power-electronics fields, such as driver ICs for plasma displays and switching power sources.
FIG. 5 is a cross-sectional structural diagram showing the element structure of an IGBT, which is a conventional high voltage semiconductor device. A low-concentration p-type silicon layer 3 (SOI active layer) is formed on a silicon substrate 1 via a buried oxide film 2. On the surface of the p-type silicon layer 3, a low-concentration n−-type drift (offset) diffusion layer 4 is selectively formed. In a region a little apart from the n−-type drift diffusion layer 4, a p-type base diffusion layer 6 is formed and on a part of the p-type base diffusion layer 6, a high-concentration n+-type emitter diffusion layer 7 is formed. On the surface of the n−-type drift diffusion layer 4, a thick LOCOS oxide film 8 is formed, and adjacent to the LOCOS oxide film 8 in the n−-type drift diffusion layer 4 on the opposite side of the p-type base diffusion layer 6, a p+-type collector diffusion layer 10 is formed. Furthermore, around the p+-type collector diffusion layer 10, an n+-type collector buffer layer 9 of a relatively high concentration is formed so as to surround the p+-type collector diffusion layer 10. On the silicon surfaces of the p-type base diffusion layer 6 and the p-type silicon layer 3 pinched by the high-concentration n+-type emitter diffusion layer 7 and the n−-type drift diffusion layer 4, a gate electrode 12 is provided via a gate oxide film 11. Furthermore, an isolating trench 13 for electrically isolating adjoining elements is formed in the p-type silicon layer 3. Finally, an interlayer insulating film 15, such as BPSG, is formed on the surface of the p-type silicon layer 3; an emitter electrode 16 is formed on the surface of the high-concentration n+-type emitter diffusion layer 7, and a collector electrode 17 is formed on the surface of the p+-type collector diffusion layer 10, to complete the IGBT.
The operation principle of thus formed IGBT will be described. At the turn-on time, when a positive voltage relative to the potential of the emitter electrode 16 is supplied to the gate electrode 12, a channel region on the surface of the p-type base diffusion layer 6 under the gate electrode 12 is in a conductive state, and electrons are implanted from the high-concentration n+-type emitter diffusion layer 7 into the n−-type drift diffusion layer 4 as shown by the arrow A1.
The p+-type collector diffusion layer 10 and the n+-type collector buffer layer 9 are forward-biased, and holes are implanted from the p+-type collector diffusion layer 10 via the n+-type collector buffer layer 9 into the n−-type drift diffusion layer 4 as shown by the arrow A2. As a result, the same number of electrons as the number of implanted holes are collected in the n−-type drift diffusion layer 4 to cause conductance modulation lowering resistance, and the IGBT is turned into the ON state.
On the other hand, at the turn-off time, if the voltage of the gate electrode 12 relative to the potential of the emitter electrode 16 is lowered, the channel region on the surface of the p-type base diffusion layer 6 under the gate electrode 12 becomes non-conductive, no electrons are implanted into the n−-type drift diffusion layer 4 from the high-concentration n+-type emitter diffusion layer 7, no conductance modulation is caused in the n−-type drift diffusion layer 4, and no current flows between the collector and the emitter. Holes remaining in the n+-type collector buffer layer 9 directly flow out into the p+-type collector diffusion layer 10 as shown by the arrow A3, and the IGBT is turned into the OFF state when flowing out is completed. The time until the holes in the n+-type collector buffer layer 9 disappear as described above is referred to as the “turn-off time”, and determines the switching speed of the element. In order to shorten the turn-off time, if the impurity concentration of the n+-type collector buffer layer 9 is elevated, the quantity of holes implanted into the n−-type drift diffusion layer 4 from the p+-type collector diffusion layer 10 can be limited.
However, the high voltage lateral semiconductor device including the IGBT as described above had the following problems. In order to improve breakdown voltage in off-time of an ordinary high voltage semiconductor element, it is required to lower the impurity concentration in the n−-type drift diffusion layer 4. However, since the concentration of electric field mainly occurs on the surface of the n−-type drift diffusion layer 4 in the IGBT formed on an SOI substrate, it is important to accelerate depletion by setting a profile to lower the impurity concentration in the vicinity of the surface.
To solve such problems, in Japanese Patent Laid-Open No. 8-236754, the surface impurity concentration in the n−-type drift diffusion layer 4 is 1×1014 to 1×1016 cm−3 and the impurity concentration in the p-type silicon layer 3 is 2×1014 to 1×1016 cm−3. Specifically, the quantity of charge in the depletion layer formed in the p-n junction between the n−-type drift diffusion layer 4 and the p-type silicon layer 3 is balanced and depletion is accelerated to improve breakdown voltage. Here, it is easily understood that the resistance value (to elevate the impurity concentration) of the n−-type drift diffusion layer 4 may be lowered in order to lower the on-resistance of the high voltage semiconductor device. However, in the conventional example, although the impurity concentration of the p-type silicon layer 3 must also be elevated to maintain the balance of depletion, since the element region other than the high voltage semiconductor element is also affected, there is limitation in elevating the impurity concentration of the p-type silicon layer 3.
Therefore, according to the patent described in Japanese Patent No. 3730283, as shown in FIG. 6, by forming a p-type base diffusion layer 5 under the n−-type drift diffusion layer 4, the balance of depletion is maintained to elevate breakdown voltage while lowering the resistance of the drift layer by changing the impurity concentration of the p-type base diffusion layer 5 without changing the concentration in the p-type silicon layer 3 even if the impurity concentration of the n−-type drift diffusion layer 4 is elevated.
Furthermore, although an IGBT wherein an n+-type collector buffer layer 9 is formed adjacent to a p+-type collector diffusion layer 10 is shown in FIG. 6, the turn-off time is as slow as about 0.5 μsec, and slower compared with an ordinary high breakdown voltage MOS transistor. The reason is that since the dose of the n+-type collector buffer layer 9 is as low as 1.0 to 2.5×1013 cm−2, the collection of implanted carriers takes a long time.
In an IGBT, breakdown voltage at on-time is an important property as well as breakdown voltage at off-time. The breakdown voltage at on-time is a voltage immediately before the collector junction is broken by avalanche breakdown when a predetermined gate voltage is supplied, and the voltage of the collector is elevated while allowing on-current determined by the gate voltage to flow. Avalanche breakdown occurs in the location where current is crowded in an element, and as a result, the element may often be destroyed.
FIG. 7 is a plan structural diagram showing the layout of the n−-type drift diffusion layer 4 against the n+-type collector buffer layer 9 including the p+-type collector diffusion layer 10 shown in FIGS. 5 and 6, and illustrating current crowding at on-time. In FIG. 7, only a corner portion of the p+-type collector diffusion layer 10 is shown; however, an IGBT built in an actual product has an optional length (gate width) in the vertical direction, and has an equivalent corner portion in the opposite side. In the surface pattern as shown in FIG. 7, when a high voltage is supplied to the p+-type collector diffusion layer 10, the region where the electric field is the highest is the corner portion where the p+-type collector diffusion layer 10 is in a convex state. The corner portion is a portion where the flow of electrons are concentrated by a large number of carriers implanted from the high-concentration emitter diffusion layer formed around the p+-type collector diffusion layer 10, and is the weakest region to breakdown voltage at on-time.